With microchip space on tiny silicon chips at a premium, but demand for faster, smaller technology on the rise, there could soon be a way to add “bandwidth” and “frequency” to the chip design paradigm by adding wireless antennas to the chips.
In an effort to develop tiny wireless networks on microchips, researchers are adding wireless radio frequency antennas which would allow information to transmit from one part of the chip to another without the use of wired interconnections, the “landlines” of the microchip world, said engineers at Drexel University.
“Much like the human intestine, wired interconnections can be very long despite their ability to be condensed into a small space,” said Dr. Baris Taskin, an associate professor in Drexel’s College of Engineering and a lead researcher on the project. “However, the sheer volume of the connections necessary to make a functional chip still takes up a great deal of area.”
Taskin’s team is designing a hybrid network-on-chip that uses antennas and wired interconnections to optimize communication speed and allow the chip to go in new and sophisticated platforms. The new chip will also use reconfigurable antenna technology developed at Drexel by Dr. Kapil Dandekar, who is Taskin’s collaborator in the research.
“A hybrid chip that utilizes both wired and wireless connections provides a more robust platform,” Taskin said. “Wired interconnections can be used as dedicated communications lines between areas that are constantly transmitting data. Antennas can eliminate a number of wired interconnections between the less-traveled paths of communication on the chip.”
The use of radio frequencies to transport data holds an additional advantage over other wireless methods used in next-generation microchips because the radio waves can travel through solids. Optical data transmission, which uses light waves, is also under development as an alternative to wired interconnections. This method requires a clear line of sight between transmitters and receivers, however, which can be a significant limiting factor in design and essentially negates its viability in 3D chip development.
A fully functional proof of concept could be ready in the next five years, according to Taskin. The biggest challenges to designing the chip are the same as those experienced in developing a telecommunications network: Making decisions about location of antennas, frequency of transmission and the amount of data it can transmit.
Successfully demonstrating the concept of wireless on-chip networking could open doors for using the technique in multi-core processors and to improve 3D chip design.